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PD - 91846A
SMPS MOSFET
IRFR1N60A
HEXFET(R) Power MOSFET
Applications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l Power Factor Correction Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current
VDSS
600V
Rds(on) max
7.0
ID
1.4A
TO-252AA
GDS
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
1.4 0.89 5.6 36 0.28 30 3.8 -55 to + 150 300 (1.6mm from case )
Units
A W W/C V V/ns C
Applicable Off Line SMPS Topologies:
l
Low Power Single Transistor Flyback
Notes
through
are on page 9
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1
7/2/01
IRFR1N60A
Static @ TJ = 25C (unless otherwise specified)
V(BR)DSS RDS(on) VGS(th) IDSS IGSS Parameter Drain-to-Source Breakdown Voltage Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 600 --- 2.0 --- --- --- --- Typ. --- --- --- --- --- --- --- Max. Units Conditions --- V V GS = 0V, ID = 250A 7.0 VGS = 10V, ID = 0.84A 4.0 V VDS = VGS, ID = 250A 25 VDS = 600V, VGS = 0V A 250 VDS = 480V, VGS = 0V, TJ = 150C 100 VGS = 30V nA -100 VGS = -30V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 0.88 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 9.8 14 18 20 229 32.6 2.4 320 11.5 130 Max. Units Conditions --- S VDS = 50V, ID = 0.84A 14 ID = 1.4A 2.7 nC VDS = 400V 8.1 VGS = 10V, See Fig. 6 and 13 --- VDD = 250V --- ID = 1.4A ns --- RG = 2.15 --- RD = 178,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 480V, = 1.0MHz --- VGS = 0V, VDS = 0V to 480V
Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
93 1.4 3.6
Units
mJ A mJ
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount)** Junction-to-Ambient
Typ.
--- --- ---
Max.
3.5 50 110
Units
C/W
Diode Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 1.4 showing the A G integral reverse --- --- 5.6 S p-n junction diode. --- --- 1.6 V TJ = 25C, IS = 1.4A, VGS = 0V --- 290 440 ns TJ = 25C, IF = 1.4A --- 510 760 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR1N60A
10
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
I D , Drain-to-Source Current (A)
1
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1
0.1
4.5V
4.5V
0.01 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 1 10
20s PULSE WIDTH TJ = 150 C
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
10
3.0
ID = 1.4A
RDS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
2.5
TJ = 150 C
2.0
1
1.5
TJ = 25 C
1.0
0.5
0.1 4.0
V DS = 100V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRFR1N60A
10000
VGS , Gate-to-Source Voltage (V)
V GS = C iss = C rs s = C oss =
0V, f = 1MH z C g s + C g d, C d sSH OR TED C gd C ds + C gd
20
ID = 1.4A VDS = 480V VDS = 300V VDS = 120V
16
C, Capacitance (pF )
1000
C iss
100
12
8
C oss
10
4
C rss
1 1 10 100 1000
A
0 0 2 4 6
FOR TEST CIRCUIT SEE FIGURE 13
8 10 12 14
V D S , D rain-to-S ourc e V oltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
10
100
OPERATION IN THIS AREA LIMITED BY RDS(on)
ISD , Reverse Drain Current (A)
I D , Drain Current (A)
TJ = 150 C
1
10 10us
100us 1 1ms
TJ = 25 C
0.1 0.4
V GS = 0 V
0.6 0.8 1.0 1.2
0.1
TC = 25 C TJ = 150 C Single Pulse
10 100
10ms 1000 10000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR1N60A
1.6
VDS VGS
RD
D.U.T.
+
I D , Drain Current (A)
1.2
RG
-VDD
10V
0.8
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
0.4
VDS 90%
0.0 25 50 75 100 125 150
TC , Case Temperature
( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 1 0.20 0.10 0.05 0.02 0.01 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR1N60A
1 5V
200
EAS , Single Pulse Avalanche Energy (mJ)
VDS
L
D R IV E R
160
ID 0.65A 0.9A BOTTOM 1.4A TOP
RG
20V tp
D .U .T
IA S
+ V - DD
120
A
0 .0 1
80
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS tp
40
0 25 50 75 100 125 150
Starting TJ , Junction Temperature ( C)
IAS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG QGD
V D S a v , Av alanche V oltage (V)
770
750
Charge
730
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
710
50K 12V .2F .3F
690
D.U.T. VGS
3mA
+ V - DS
670 0.0 0.4 0.8 1.2 1.6
A
I av , Av alanche Current (A)
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage Vs. Avalanche Current
6
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IRFR1N60A
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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IRFR1N60A
Package Outline
TO-252AA Outline Dimensions are shown in millimeters (inches)
6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1 .0 2 (.0 4 0 ) 1 .6 4 (.0 2 5 ) 1 2 3 -B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 3X 1 .1 4 (.0 4 5 ) 2 X 0 .7 6 (.0 3 0 ) 2 .2 8 (.0 9 0 ) 4 .5 7 (.1 8 0 ) 0 .8 9 (.0 3 5 ) 0 .6 4 (.0 2 5 ) 0 .2 5 (.0 1 0 ) M AMB 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 ) 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 )
1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN
0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) N O TE S : 1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X . + 0 .1 6 (.0 0 6 ).
Part Marking Information
TO-252AA (D-PARK)
E XA M P L E : TH IS IS A N IR F R 1 2 0 W IT H A S S E M B L Y LOT COD E 9U1P
IN TE R N A TIO N A L R E C T IF IE R LOG O
A
IR F R 120 9U 1P
F IR S T P O R T IO N O F PA RT NUM B ER
A SSEMB LY LO T COD E
S E C O N D P O R TIO N O F P ART NU M B ER
8
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IRFR1N60A
Tape & Reel Information
TO-252AA
TR TRR TRL 1 6 .3 ( .6 4 1 ) 1 5 .7 ( .6 1 9 ) 1 6 .3 ( .6 4 1 ) 1 5 .7 ( .6 1 9 )
1 2 .1 ( .4 7 6 ) 1 1 .9 ( .4 6 9 )
F E E D D IR E C T IO N
8 .1 ( .3 1 8 ) 7 .9 ( .3 1 2 )
F E E D D IR E C T IO N
NO TES : 1 . C O N T R O L L IN G D IM E N S IO N : M IL L IM E T E R . 2 . A L L D IM E N S IO N S A R E S H O W N IN M IL L IM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 8 1 & E IA -5 4 1 .
1 3 IN C H
16 m m N O TE S : 1 . O U T L IN E C O N F O R M S T O E IA -4 8 1 .
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25C, L = 95mH
RG = 25, IAS = 1.4A. (See Figure 12)
ISD 1.4A, di/dt 180A/s, VDD V(BR)DSS,
TJ 150C ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936 http://www.irf.com/ Data and specifications subject to change without notice. 7/01
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